1. Field of the Invention
This invention relates to memory within computer systems, and more specifically, to error correction systems for detecting and correcting errors that may be present in data stored or transmitted to and from system memory.
2. Description of the Relevant Art
For data transmissions occurring within a given computer system, there always exists the possibility that the transmitted data includes an error. This is also true when the source of the transmitted data is a dynamic random access memory (DRAM). The majority of errors that occur in a DRAM chip are soft errors, which are correctable. Hard errors may occur as well, and some hard errors may be correctable, but their occurrence is typically less frequent than the occurrence of soft errors. Two primary sources of soft errors are alpha particles and cosmic rays. Since a DRAM stores a given bit via a charge, an alpha particle or cosmic ray can alter this charge, thereby changing the contents of a given memory cell.
As the amount of main memory in computer systems has continued to increase, the frequency of soft errors has increased correspondingly. Soft errors, if left uncorrected, can have adverse effects on system performance, corrupting data and even causing system crashes. One measure of the possibility of such failure is referred to as Mean Time between Failures (MTBF). Uncorrected soft errors can reduce the MTBF of a given computer system.
In order to counter the presence of errors, many computers employ error correction circuitry. Such circuitry is used to implement error correction codes (ECCs), which are used to detect and correct errors within a computer system. There are many different types of ECCs. Some of the more commonly used codes are referred to as Hamming codes, although many others have been developed. In some error correction systems, a bit pattern, such as one representing an ASCII character, is recoded with redundant bits, more commonly referred to a check bits. Groups of check bits may be referred to as check words, and each data block stored in a DRAM may be protected by at least one check word.
Parity is another element of many error correction codes. Even parity is defined as adding a check bit so that the total number of logic ones in a given bit pattern is even, while odd parity involves adding a check bit so that the total number of logic ones is odd. In a system where even parity is in use, the receipt of a word (including check bits) which contains an odd number of logic ones automatically indicates the presence of an error in the data. Receipt of a word containing an even number of logic ones in an odd parity system will also indicate the presence of an error.
Many error correction schemes can correct only one error within a given data word. Some error correction schemes allow the detection of two errors, but these schemes are usually unable to unambiguously correct both of them. As previously mentioned, many soft errors in a DRAM are caused by cosmic rays or Alpha particles. Alpha particles are localized phenomena, and in many cases, can alter the contents of multiple bits in the general area in which they occur. Similarly, cosmic rays, while not a localized phenomena, can nevertheless bombard a semiconductor memory with protons and neutrons, randomly altering the stored bits. Since a number of error correction schemes assign physically adjacent check bits within the DRAM to a given check word, there is an increased possibility of uncorrectable multi-bit soft errors occurring within a given check word. Furthermore, data bits protected by a given check word may be altered in the same manner.
The relationship between DRAM cell architecture and DRAM input/output (I/O) architecture may have an affect on the manner in which given check bits are assigned to check words. For example, in some DRAM chips with sixteen data lines D0-D15, the cell layout may result in cells connected to a data line D15 being physically adjacent to cells connected data line D0, although these two bits are not logically adjacent. In other DRAM chips, D0 may be adjacent to D1, D1 is adjacent to D2, and so on. Check bits on these data lines are often assigned to the same check word. Consequently, the actual layout of the DRAM cell architecture can affect the ability to detect and/or correct data errors.
FIG. 1 illustrates one prior art example of a memory array within a DRAM, wherein check bits which are assigned to a same check word are stored in non-adjacent locations. When certain phenomena occur, such as alpha particle radiation, multiple adjacent bits stored in a memory array can be altered, causing multi-bit errors. As may be appreciated, multi-bit errors are generally more difficult to detect and correct than single-bit errors. Since there is a likelihood that soft and/or hard errors will cause physically adjacent cells to provide erroneous data, associating check bits with check words in this manner results in multi-bit errors appearing as single-bit errors to an error correction subsystem. Similarly, the likelihood of multi-bit errors occurring in the same check word may be reduced.
In the example of FIG. 1, a memory array 100 is shown to include storage for sixteen bits. Four rows R1-R4 104 and four columns C1-C4 102 are shown, with the intersection of each row and column generally representing a bit location. For example, four bit locations are labeled as 120A-120D. Also shown are four checkwords, Checkword 1 130, Checkword 2 132, Checkword 3 134, and Checkword 4 136. For convenience, each bit location in the array 100 is labeled with a number which identifies the checkword (130, 132, 134, or 136) to which it is assigned. For example, bit locations 150 and 152 are assigned to checkword 1 130, and bit locations 154 and 156 are assigned to checkword 2 132. As can be seen in the example, bit locations assigned to a given checkword are not adjacent to any other bit locations assigned to the same checkword.
Generally speaking, a memory module typically includes a printed circuit board upon which a plurality of DRAM chips are mounted. Some of these DRAM chips are configured to store data words, while others store check bits associated with given data words. Each data word is protected by a number of check bits forming a check word. These check bits are generated according to a predetermined error correction scheme, such as a Hamming code. A group of check bits is referred to a check word. The check bits are stored in DRAM chips in such a manner that each check bit of a given check word is stored in a physically non-adjacent memory cell with respect to every other check bit in the given check word. Typically, each check bit from a given DRAM chip will be assigned to a different check word.
During a memory access, a data word is accessed, and check words associated with the accessed data word are received by an error correction subsystem. The error correction subsystem will then use the check words to check for the presence of an error, according to the predetermined error correction scheme. Since each of the check bits from a given DRAM chip is assigned to a different check word, multi-bit errors from a given DRAM chip will appear as a plurality of single-bit errors, which are generally easier to detect and correct. Furthermore, since check bits from a given DRAM are assigned to different check words, the likelihood of multiple errors occurring in the same check word may be reduced.
While the approach depicted in FIG. 1 may provide additional benefits as compared to other approaches, it is not completely immune from various other types of problems. For example, one type of failure which may occur involves the failure of a word line. Referring back to FIG. 1, assume that each of rows 104 represent a word line which is activated during a memory access. If, for example, row/word line R1 were to fail, two check bits for each of checkword 1 130, and checkword 3 134 would fail. Consequently, the error would generally not be correctable.
A method to reduce the possibility of uncorrectable multi-bit errors from degrading system operation would be desirable. It would be further desirable to make multi-bit soft errors appear as single-bit soft errors, thereby making the errors easier to correct.